1. Field of the Invention
The present invention relates to the field of computer-aided design and more particularly to computer-aided design systems using event driven simulation algorithms.
2. Prior Art
Computer-aided design has become a commonly used tool in the design of complex electrical designs. Computer-aided design work stations are almost a necessity in designing high density electrical circuits and semiconductor device layouts. These computer-aided design work stations not only provide a design tool but are capable of providing diagnostics to detect design errors quickly.
Typically, the more advanced and large computer-aided design work stations for logic simulation are capable of simulating circuits having over a million components. Instead of evaluating every input and output, event driven algorithms evaluate only those inputs and outputs which change their states from one time period to the next. One such digital computer system which implements an event driven simulation algorithm is described in U.S. patent application Ser. No. 594,533; filed Mar. 28, 1984; entitled Digital Computer for Implementing Event Driven Simulation Algorithm; which issued as U.S. Pat. No. 4,751,637 on June 14, 1988, and is implemented in a work station commercially available and sold under the trademark "MEGALOGICIAN" by Daisy Systems Corporation of Mountain View, California. However, this prior art system utilizes a microcodable simulation processor which tends to limit the processing speed capability due to a single ALU used with each processor.
The present invention implements an event driven simulation algorithm by utilizing a more complex architecture which permits a large number of processors to operate simultaneously in parallel, as well as a new streamlined hardwired processor, for providing simulation capability at a much faster pace.
Prior art references known to the Applicant which disclose special purpose computers for implementing simulation algorithms are:
(i) "A Logic Simulation Machine" by Abramovici, M. et al; IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. CAD-2, No. 2; April 1983. The present invention implements an algorithm similar to that described in this article. However, the partitioning used in the present invention is substantially different than that discussed in the article.
(ii) "ZYCAD Logic Evaluator" as described in ZYCAD Corporation's manual dated November, 1982. This apparatus employs different partitioning than the present invention. Moreover, it does not offer the flexibility of the presently described invention where the computer is microcode programmable.
(iii) "Parallel Processing Interactively Simulates Complex VSLI Logic" by Howard, J. et al; Electronics Dec. 15, 1983; beginning at p. 147. This article describes the implementation of a different algorithm which is not event driven. Different architecture and partitioning are employed. (Applicant does not concede that this particular article is prior art, however, Applicant believes that there are prior art computers employing the teachings of this article.)
(iv) U.S. Pat. No. 4,527,249.